Semiconductor wafer processing apparatus

ABSTRACT

A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.

FIELD OF THE INVENTION

[0001] This invention relates to a semiconductor wafer processingapparatus for grinding a semiconductor wafer to thin it.

DESCRIPTION OF THE PRIOR ART

[0002] In a process for manufacturing a semiconductor wafer for use in asemiconductor device, grinding is performed to decrease the thickness ofthe semiconductor wafer as thin semiconductor devices are becomingpredominant. The grinding is carried out by mechanical grinding of aback side of the semiconductor wafer opposite to its face side after acircuit pattern has been formed on the face side. On the surface of thesemiconductor wafer after mechanical grinding, there is a damaged layerembrittled by microcracks formed by mechanical grinding. The damagedlayer is known to include the microcracks and impair the fracturestrength of the semiconductor wafer. Thus, a conventional semiconductorhas been used with such a thickness that the semiconductor is notaffected by a decrease in the fracture strength due to the damagedlayer.

[0003] In response to the light weight and compact size of electronicequipment, moves for thinning semiconductor devices to meet demands fortheir light weight and compact size have become brisk. Along this line,further thinning of semiconductor wafers has also been demanded. Toreduce the thickness of the semiconductor wafer, however, the influenceof the decrease in the fracture strength due to the damaged layer isbecoming nonnegligible. To solve this problem, processing to a smallthickness (hereinafter referred to as thinning), including removal ofthe damaged layer, is necessary. However, any appropriate apparatus,which can perform a series of thinning steps, ranging from mechanicalgrinding of the semiconductor wafer to removal of the damaged layer, hasnot existed.

SUMMARY OF THE INVENTION

[0004] Under these circumstances, the present invention aims to providea semiconductor wafer processing apparatus and a semiconductor waferprocessing method which can perform a series of thinning steps, rangingfrom mechanical grinding of a semiconductor wafer to removal of itsdamaged layer.

[0005] According to the present invention, there is provided asemiconductor wafer processing apparatus for grinding a surface of asemiconductor wafer to thin the semiconductor wafer, comprising agrinding portion for mechanically grinding the semiconductor wafer, awafer cleaning portion for cleaning the semiconductor wafer aftermechanical grinding, a damaged layer removal treatment portion forremoving a damaged layer, caused to the semiconductor wafer bymechanical grinding, after cleaning by the wafer cleaning portion, and awafer transport mechanism for transferring the semiconductor waferbetween the grinding portion, the wafer cleaning portion, and thedamaged layer removal treatment portion.

[0006] It is preferred to include a precenter portion for centering thesemiconductor wafer, and supply the semiconductor wafer, which has beencentered by the precenter portion, to the grinding portion by the wafertransport mechanism. An stocker can be provided for accommodating thesemiconductor wafer before processing which is to be supplied to thegrinding portion and/or the semiconductor wafer after processing whichhas been withdrawn from the damaged layer removal treatment portion. Thewafer transport mechanism preferably includes a robot mechanism on apolar coordinate system. Preferably, the wafer transport mechanism alsoincludes a before-cleaning transport portion for withdrawing thesemiconductor wafer after mechanical grinding from the grinding portion,and passing the semiconductor wafer on to the wafer cleaning portion,and an after-cleaning transport portion for withdrawing thesemiconductor wafer after cleaning from the wafer cleaning portion, andpassing the semiconductor wafer on to the damaged layer removaltreatment portion. The damaged layer removal treatment portion may be aplasma treatment portion for etching the damaged layer by plasmatreatment. The damaged layer removal treatment portion may be a wetetching treatment portion for etching the damaged layer with a chemicalliquid. Preferably, the wafer transport mechanism comprises a firstwafer transport portion for holding the semiconductor wafer from theprecenter portion and bringing the semiconductor wafer onto the grindingportion, a second wafer transport portion for withdrawing thesemiconductor wafer ground by the grinding portion and transporting thesemiconductor wafer to the wafer cleaning portion, and a third wafertransport portion having a robot mechanism on a polar coordinate systemfor transferring the semiconductor wafer between the precenter portion,the wafer cleaning portion, and the damaged layer removal treatmentportion, and the damaged layer removal treatment portion is disposed ina third quadrant and a fourth quadrant of an orthogonal coordinatesystem in which an origin of the polar coordinate system of the robotmechanism is a common origin and a direction of the grinding portion isa Y-axis positive direction, and such that the origin of the polarcoordinate system is positioned on a line of extension of asemiconductor wafer carry-in and carry-out center line of the damagedlayer removal treatment portion. The stocker for accommodating thesemiconductor wafer before processing which is to be supplied to thegrinding portion and/or the semiconductor wafer after processing whichhas been withdrawn from the damaged layer removal treatment portion ispreferably provided at a position at which the wafer can be brought inand brought out by the third wafer transport portion. The cleaningportion can be disposed in one of the first quadrant and the secondquadrant of the orthogonal coordinate system. The precenter portion canbe disposed in a quadrant of the coordinate system on a side opposite tothe cleaning portion, with the Y-axis of the coordinate system beinginterposed between the precenter portion and the cleaning portion.

[0007] According to the present invention, there is further provided asemiconductor wafer processing method for thinning a semiconductor waferto a target thickness, including the steps of mechanically grinding aside of the semiconductor wafer opposite to a surface thereof, where acircuit has been formed, by a grinding portion; withdrawing thesemiconductor wafer after mechanical grinding from the grinding portion,and passing the semiconductor wafer on to the wafer cleaning portion;cleaning the semiconductor wafer passed on to the wafer cleaningportion; withdrawing the semiconductor wafer after cleaning from thewafer cleaning portion and passing the semiconductor wafer on to adamaged layer removal treatment portion; and removing a damaged layer,caused by the mechanical grinding, in the damaged layer removaltreatment portion.

[0008] The damaged layer removal treatment portion may be a plasmatreatment portion for etching the damaged layer by plasma treatment. Itis preferred to grind the semiconductor wafer by mechanical grinding toa thickness being a sum of the target thickness and a dry etching marginset in a range of 3 μm to 50 μm, and remove a remainder of thesemiconductor wafer by dry etching using plasma treatment. Thesemiconductor wafer may consist essentially of silicon. After thesemiconductor wafer is ground by the mechanical grinding, thesemiconductor wafer is preferably cleaned with a liquid before dryetching is performed. The liquid may be water. The damaged layer removaltreatment portion may be a wet etching treatment portion for etching thedamaged layer with a chemical liquid. Preferably, mechanical grindingand removal of the damaged layer are performed, with a protective filmbeing formed on the surface of the semiconductor wafer where the circuithas been formed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a perspective view of a semiconductor wafer processingapparatus as an embodiment of the present invention;

[0010]FIG. 2 is a plan view of the semiconductor wafer processingapparatus as the embodiment of the present invention;

[0011]FIG. 3 is a perspective view of a wafer stocker of thesemiconductor wafer processing apparatus as the embodiment of thepresent invention;

[0012]FIG. 4 is a perspective view of the wafer stocker of thesemiconductor wafer processing apparatus as the embodiment of thepresent invention;

[0013]FIG. 5 is a partial plan view of the semiconductor waferprocessing apparatus as the embodiment of the present invention;

[0014]FIG. 6 is a side view of a grinding portion of the semiconductorwafer processing apparatus as the embodiment of the present invention;

[0015]FIG. 7 is a sectional view of a wafer cleaning portion of thesemiconductor wafer processing apparatus as the embodiment of thepresent invention;

[0016]FIG. 8 is a sectional view of a plasma treatment portion of thesemiconductor wafer processing apparatus as the embodiment of thepresent invention;

[0017] FIGS. 9(a) and 9(b) are each a process explanation drawing of asemiconductor wafer processing method as an embodiment of the presentinvention;

[0018] FIGS. 10(a) and 10(b) are each a process explanation drawing of asemiconductor wafer processing method as an embodiment of the presentinvention; and

[0019]FIG. 11 is a flow chart for cleaning of a semiconductor wafer inthe semiconductor wafer processing method as the embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Embodiments of the present invention will be described byreference to the accompanying drawings.

[0021] The entire structure of a semiconductor wafer processingapparatus will be described with reference to FIGS. 1 and 2. In FIGS. 1and 2, a third wafer transport portion 3 composed of a robot mechanismon a polar coordinate system is disposed on a front half 1 a of an uppersurface of a base portion 1. A wafer stocker 2 having magazines (wafercassettes) 2A, 2B, a first plasma treatment portion 4A, a second plasmatreatment portion 4B, a precenter portion 5, and a wafer cleaningportion 10 are disposed radially around the third wafer transportportion 3. The magazines 2A, 2B, first plasma treatment portion 4A,second plasma treatment portion 4B, precenter portion 5, and wafercleaning portion 10 are arranged in a range in which a wafer can bebrought in and out by the third wafer transport portion 3.

[0022] The magazines 2A, 2B of the wafer stocker 2 accommodate aplurality of semiconductor wafers before and after processing. The firstplasma treatment portion 4A and the second plasma treatment portion 4Bremove a damaged layer, caused by mechanical grinding on the surface ofa semiconductor wafer 11, by the etching action of a plasma generated ina vacuum atmosphere. Thus, the first plasma treatment portion 4A and thesecond plasma treatment portion 4B constitute a damaged layer removaltreatment portion for the semiconductor wafer.

[0023] The precenter portion 5 performs a centering action forpreliminarily aligning the semiconductor wafer to be passed on to agrinding portion 6 to be described later on. The wafer cleaning portion10 cleans the semiconductor wafer, ground by the grinding portion 6,with a cleaning fluid.

[0024] The grinding portion 6 for mechanically grinding thesemiconductor wafer 11 is disposed on a rear half 1 b of the uppersurface of the base portion 1. The grinding portion 6 has a wall portion6 a erected on the upper surface of the base portion 1, and a firstgrinding unit 8A and a second grinding unit 8B are disposed on a frontside surface of the wall portion 6 a. The first grinding unit 8A and thesecond grinding unit 8B perform rough grinding and finish grinding,respectively, of the semiconductor wafer 11. A turn table 7 surroundedby a combing 6 b is disposed below the first grinding unit 8A and secondgrinding unit 8B. The turn table 7 makes an index rotation to positionthe semiconductor wafer, an object to be ground, relative to the firstgrinding unit 8A and second grinding unit 8B while holding thesemiconductor wafer.

[0025] Ahead of the grinding portion 6, a first wafer transport portion9A and a second wafer transport portion 9B are disposed. The first wafertransport portion 9A brings the semiconductor wafer, aligned at theprecenter portion 5, into the grinding portion 6. The second wafertransport portion 9B brings the semiconductor wafer after mechanicalgrinding out of the grinding portion 6. Thus, the aforementioned firstwafer transport portion 9A, second wafer transport portion 9B, and thirdwafer transport portion 3 constitute a wafer transport mechanism fortransferring the semiconductor wafer 11 between the grinding portion 6,wafer cleaning portion 10, first plasma treatment portion 4A and secondplasma treatment portion 4B, supplying the semiconductor wafer 11 to thegrinding portion 6, and withdrawing the semiconductor wafer 11 after dryetching from the first plasma treatment portion 4A and second plasmatreatment portion 4B.

[0026] Layout of the respective members on the base portion 1 will bedescribed. As shown in FIG. 2, an XY orthogonal coordinate system,having an origin O of the polar coordinate system of the robot mechanismof the third wafer transport portion 3 as a common origin, and having adirection of the grinding portion 6 as a Y-axis positive direction, isset on the base portion 1. In this orthogonal coordinate system, theprecenter portion 5, first wafer transport portion 9A and first grindingunit 8A are in the first quadrant, the second grinding unit 8B, secondwafer transport portion 9B and wafer cleaning portion 10 are in thesecond quadrant, the first plasma treatment portion 4A and magazine 2Aare in the third quadrant, and the second plasma treatment portion 4Band magazine 2B are in the fourth quadrant.

[0027] In this layout, the magazines 2A, 2B, first plasma treatmentportion 4A, second plasma treatment portion 4B, precenter portion 5 andwafer cleaning portion 10 are arranged such that their wafer carry-inand carry-out directions agree with the direction of the origin O of thepolar coordinate system. The first plasma treatment portion 4A andsecond plasma treatment portion 4B, in particular, are required to bedirected and positioned accurately during carry-in and carry-out of thewafer. Thus, their positions and directions of disposition are set suchthat the origin O is accurately positioned on lines of extension La, Lbof their wafer carry-in and carry-out center lines.

[0028] The constitutions and functions of the respective members will bedescribed sequentially, starting with the third wafer transport portion3. In FIG. 2, the third wafer transport portion 3 is mounted in aconcave 1 c formed in the center of the front half 1 a. The robotmechanism on the polar coordinate system is disposed on a base member 3a of the third wafer transport portion 3. The base member 3 a can beturned 360 degrees by a drive mechanism (not shown) on the base portion1 about the origin O of the polar coordinate system to control thedirection of the robot mechanism freely.

[0029] The robot mechanism is constituted by coupling a second turningarm 14 b to a first turning arm 14 a extending laterally of a verticallyexpansible arm shaft (not shown) erected on the base member 3 a, andmounting a wafer holding portion 17 to a front end of the second turningarm 14 b. The wafer holding portion 17 has a bifurcated fork-shapedmember 17 b having attraction holes 17 a provided on an upper surfacethereof (see FIG. 4). The wafer holding portion 17 rotates about itsaxis by a hand rotation mechanism 15, and the inclination of the waferholding portion 17 is controlled by a wrist mechanism 16. Moreover, thewafer holding portion 17 can be moved forward and backward horizontallyby turning the first turning arm 14 a and the second turning arm 14 b.

[0030] Upon driving of the respective members of the robot mechanism,the wafer holding portion 17 moves relative to the objects for transferof the wafer thereto and therefrom, such as the magazines 2A, 2B, firstplasma treatment portion 4A, second plasma treatment portion 4B,precenter portion 5, and wafer cleaning portion 10. As stated earlier,these respective objects of wafer transfer are arranged such that theirwafer carry-in and carry-out directions agree with the direction of theorigin O of the polar coordinate system. Thus, the semiconductor wafer11 can be transferred between these objects of wafer transfer by thewafer holding portion 17 of the robot mechanism.

[0031] That is, the base member 3 a is turned, whereby the wafer holdingportion 17 can be pointed in the wafer carry-in and carry-out directionsof the objects of wafer transfer. The wafer holding portion 17 is movedforward horizontally by the first turning arm 14 a or second turning arm14 b, and can thus be accessed to each member. The wafer holding portion17 is also moved upward or downward by driving the arm shaft (notshown). By a combination of this upward or downward movement, andswitching ON/OFF of vacuum attraction through the attraction holes 17 aof the wafer holding portion 17, the semiconductor wafer 11 can beattracted to or released from the wafer holding portion 17. By drivingthe hand rotation mechanism 15, moreover, the semiconductor wafer 11attracted to and held by the attraction holes 17 a of the wafer holdingportion 17 (see FIG. 4) can be turned upside down.

[0032] As described above, the respective members, which the wafer istransferred to and from, are arranged radially around the third wafertransport portion 3 using the robot mechanism on the polar coordinatesystem. Employment of this arrangement makes it possible to cover theplurality of the targets of wafer transfer by a single robot mechanism,and actualize a semiconductor wafer processing apparatus with high workefficiency and of a compact size.

[0033] Next, the wafer stocker 2 will be described. As shown in FIGS. 1and 2, the wafer stocker 2 has two magazines 2A and 2B for waferaccommodation. The magazines 2A, 2B accommodate many semiconductorwafers to be thinned. As shown in FIGS. 3 and 4, the magazines 2A, 2Bhave a structure in which shelf members 13 are provided in many stagesinside a housing 12, and a semiconductor wafer 11 is borne on each ofthe shelf members 13.

[0034] The semiconductor wafer 11 consists essentially of silicon, andhas a plurality of semiconductor devices built therein. A protectivefilm 11 a is formed on the surface of the semiconductor wafer 11 onwhich a circuit has been formed (see FIG. 10(b)). The protective film 11a protects the circuit pattern of the semiconductor wafer 11, andfunctions to reinforce the semiconductor wafer 11 and enhance itsfracture strength. The protective film 11 a is formed by pasting a resinsheet to the circuit-formed surface of the semiconductor wafer 11. Inaccommodating the semiconductor wafer 11 in the magazine 2A or 2B, thesemiconductor wafer 11 is borne on the shelf member 13 with theprotective film 11 a facing upward.

[0035] The actions of the wafer holding portion 17 for withdrawing andaccommodating the semiconductor wafer 11 from and into the magazines 2A,2B will be described. For withdrawal, the wafer holding portion 17 isinserted into a space above the semiconductor wafer 11 accommodated inthe magazine 2A (2B), with the attraction holes 17 a facing downward, asshown in FIG. 3. Then, the wafer holding portion 17 is lowered until itcontacts the upper surface of the semiconductor wafer 11. In this state,vacuum attraction through the attraction holes 17 a is carried out,whereby the semiconductor wafer 11 is attracted to and held by the lowersurface of the wafer holding portion 17. Then, the wafer holding portion17 is raised again, and pulled out of the magazine 2A (2B). As a result,the semiconductor wafer 11 is withdrawn while being attracted to andheld by the lower surface of the wafer holding portion 17.

[0036]FIG. 4 shows an accommodating action for returning thesemiconductor wafer 11 into the magazine 2A (2B). For the accommodatingaction, the semiconductor wafer 11, which has been attracted to and heldby the upper surface of the wafer holding portion 17 with the thinnedsurface of the semiconductor wafer 11 facing upward, is turned upsidedown by rotating the wafer holding portion 17 about its axis. By sodoing, the protective film 11 a is directed upward, and thesemiconductor wafer 11 is accommodated in this posture into the magazine2A (2B). At this time, the same semiconductor wafer 11 is returned tothe same location where it was accommodated before processing.

[0037] This returning is performed by inserting the wafer holdingportion 17, which has held the semiconductor wafer 11 on its uppersurface, into the magazine 2A (2B), then releasing vacuum attraction,and then lowering the wafer holding portion 17. That is, during thislowering action, the fork-shaped member 17 b of the wafer holdingportion 17 passes through a notch 13 a downward, with the semiconductorwafer 11 being borne on the shelf member 13, as shown in FIG. 4. Thewafer holding portion 17 is pulled out of the magazine, wherebyaccommodation of the semiconductor wafer 11 is completed.

[0038] Next, the precenter portion 5 will be described with reference toFIG. 5. The precenter portion 5 is designed to align the semiconductorwafer 11 to be supplied to the grinding portion 6. In FIG. 5, theprecenter portion 5 has a circular bearing table 20. A removed portion21 (see the hatching) having an upper surface partially removed incorrespondence with the shape of the wafer holding portion 17 is formedon the upper surface of the bearing table 20. The depth of the removedportion 21 is set to be a depth in which the wafer holding portion 17can be accommodated in the removed portion 21.

[0039] The semiconductor wafer 11 is carried into the precenter portion5 in the following manner: The wafer holding portion 17 holding thesemiconductor wafer 11 on its upper surface is moved above the bearingtable 20 until the horizontal position of the wafer holding portion 17aligns with the removed portion 21. Then, the wafer holding portion 17is lowered to a height position at which it is accommodated into theremoved portion 21. By this measure, the semiconductor wafer 11 is borneon the bearing table 20. Then, the wafer holding portion 17 is retreatedfrom inside the removed portion 21, whereby carry-in of thesemiconductor wafer 11 is completed.

[0040] In the bearing table 20, a plurality of grooved portions 22 areprovided radially toward the center at 120-degree equal angularpositions. Each of the grooved portions 22 has a positioning pawl 22 awhich is movable along the direction of the groove. The positioning pawl22 a is moved toward the center of the bearing table 20, with thesemiconductor wafer 11 being borne on the bearing table 20, whereby thesemiconductor wafer 11 is aligned with the central position of thebearing table 20. That is, the precenter portion 5 performs centering ofthe semiconductor wafer 11 to be supplied to the grinding portion 6.

[0041] The first wafer transport portion 9A is disposed adjacent to theprecenter portion 5. The first wafer transport portion 9A is constitutedby mounting an attracting head 25A to a front end of a transport arm24A, which is turned and driven upward or downward by an arm drivemechanism 23, as shown in FIG. 5. When the attracting head 25A is movedabove the semiconductor wafer 11 of the precenter portion 5 and thenlowered, the attracting head 25A attracts and holds the semiconductorwafer 11. Then, the transport arm 24A is raised and turned toward thegrinding portion 6, whereby the semiconductor wafer 11 is carried intothe grinding portion 6, and moved to a wafer transfer station (to bedescribed later on).

[0042] Next, the grinding portion 6 will be described with reference toFIGS. 2 and 6. As shown in FIGS. 2 and 6, the turn table 7 is disposedon the upper surface of the base portion 1. The turn table 7 can make anindex rotation about its central shaft, and has three chuck tables 7 aprovided at 120-degree equal angular positions which are indexpositions.

[0043] Each chuck table 7 a receives the semiconductor wafer 11 from thetransport arm 24A of the first wafer transport portion 9A at the wafertransfer station (a left-hand index position in FIG. 6). The chuck table7 a has the semiconductor wafer 11 attracted to and held on an uppersurface thereof, and is rotatable about its axis.

[0044] The first grinding unit 8A and the second grinding unit 8B areprovided on the side surface of the wall portion 6 a erected at theright end of the upper surface of the base portion 1. The first grindingunit 8A and the second grinding unit 8B are arranged in the horizontaldirection at positions corresponding to the index positions of the turntable 7. The index positions below the first grinding unit 8A and thesecond grinding unit 8B define a rough grinding station and a finishgrinding station, respectively.

[0045] The first grinding unit 8A and the second grinding unit 8B eachhave a rotary drive portion 30. A grindstone 31A or 31B for roughgrinding or finish grinding the semiconductor wafer 11 is mounted on thelower surface of the rotary drive portion 30. For rough grinding, agrindstone of about #500 is used. For finish grinding, a grindstone of#3000 to #4000 is generally used. The first grinding unit 8A and thesecond grinding unit 8B each ascend and descend by the action of abuilt-in upwardly and downwardly moving mechanism.

[0046] As shown in FIG. 6, the chuck table 7 a holding the semiconductorwafer 11 is moved to the index position (grinding position) below thefirst grinding unit 8A (or second grinding unit 8B). In this state, thegrindstone 31A (or 31B) is lowered to contact the upper surface of thesemiconductor wafer 11. The grindstone 31A (or 31B) is rotated by therotary drive portion 30 to grind the upper surface of the semiconductorwafer 11.

[0047] When the chuck table 7 a is located at the grinding positionbelow the first grinding unit 8A or the second grinding unit 8B, thechuck table 7 a is rotated by a drive mechanism (not shown). Therotation of the chuck table 7 a and the rotation of the grindstone 31Aor 31B are combined, whereby the upper surface of the semiconductorwafer 11 is ground uniformly during grinding.

[0048] During the grinding, a grinding liquid is supplied to the groundsurface of the semiconductor wafer 11 by grinding liquid supply means(not shown). The grinding liquid is accumulated in the combing 6 bprovided on the upper surface of the base portion 1 so as to surroundthe turn table 7, and is discharged to the outside. The semiconductorwafer 11 after grinding is moved to the wafer transfer position bymoving the chuck table 7 a by the index rotation of the turn table 7.Then, the semiconductor wafer 11 is carried out by the transport arm 24Bof the second wafer transport portion 9B.

[0049] Next, the structure of the wafer cleaning portion 10 will bedescribed with reference to FIG. 7. The wafer cleaning portion 10 isdisposed on a side opposite to the precenter portion 5, with the Y-axisof the orthogonal coordinate system being interposed between the wafercleaning portion 10 and the precenter portion 5. In FIG. 7 showing theBB section of FIG. 2, an opening 35 a is provided in an upper part of abox-shaped cleaning frame portion 35 by partially cutting out the frontsurface and two side surfaces of the frame portion 35. The opening 35 ahas a size which allows the entry and exit of the second wafer transportportion 9B holding the semiconductor wafer 11. At the bottom 35 b of thecleaning frame portion 35, there are provided an opening 35 c fordrainage, and a bearing boss 35 d of an upwardly protruding shape. Abearing 38 is fitted into the bearing boss 35 d, and a rotary supportportion 40 is bound to an upper part of a vertical shaft portion 39rotatably supported by the bearing 38.

[0050] A plurality of attraction holes 40 a are provided in a horizontalupper surface of the rotary support portion 40, and the attraction holes40 a communicate with a suction hole 39 a provided in the shaft portion39. Vacuum suction is performed through the suction hole 39 a by drivinga suction control portion 46 connected to the suction hole 39 a, withthe semiconductor wafer 11 being borne on the upper surface of therotary support portion 40. By this vacuum suction, the semiconductorwafer 11 is attracted to and held by the upper surface of the rotarysupport portion 40.

[0051] A pulley 41 is bound to-a lower part of the shaft portion 39, anda belt 42 is looped between the pulley 41 and a pulley 43 bound to arotating shaft 44 a of a motor 44. The motor 44 is driven by a motordrive portion 45. The shaft portion 39 is rotated by driving the motor44. Thus, the semiconductor wafer 11 held by the rotary support portion40 spins.

[0052] Inside the cleaning frame portion 35, a tubular cover portion 36of a shape surrounding the semiconductor wafer 11 is mounted so as to bemovable upward and downward. A rod 37 a of a cylinder 37 is bound to aflange portion 36 a provided in an upper part of the cover portion 36.The cover portion 36 moves upward and downward upon driving of thecylinder 37. When the cover portion 36 has ascended, the flange portion36 a is located at a position at which it contacts a ceiling surface ofthe cleaning frame portion 35, whereby the opening 35 a is closed withthe cover portion 36.

[0053] On the ceiling surface of the cleaning frame portion 35, acleaning fluid nozzle 47 and an air nozzle 49 are disposed, with theirejecting direction facing downward. The cleaning fluid nozzle 47 isconnected to a cleaning fluid supply portion 48 for supplying a cleaningfluid such as pure water. By driving the cleaning fluid supply portion48, a cleaning fluid is ejected from the cleaning fluid nozzle 47 towardthe upper surface of the semiconductor wafer 11 supported by the rotarysupport portion 40.

[0054] At this time, the semiconductor wafer 11 is spinning upon drivingof the motor 44. The cleaning fluid jetted at the center of thesemiconductor wafer 11 flows toward the outer edge of the semiconductorwafer 11 by a centrifugal force. As a result, foreign matter adhering tothe upper surface of the semiconductor wafer 11 is removed together withthe cleaning fluid, and accumulated on the bottom surface of thecleaning frame portion 35. Then, the foreign matter is guided, togetherwith the cleaning fluid, to waste water treatment equipment (not shown)through the opening 35 c and a drainage pipe 35 e.

[0055] The air nozzle 49 is connected to an air supply portion 50, andair is ejected downward through air holes 49 a of the air nozzle 49 bydriving the air supply portion 50. Thus, drops of the cleaning fluidadhering to and remaining on the upper surface of the semiconductorwafer 11 after cleaning are removed, so that hydro-extraction and dryingare carried out. The above-described actions are performed bycontrolling the cylinder 37, motor drive portion 45, suction controlportion 46, cleaning fluid supply portion 48 and air supply portion 50by a control portion (not shown) in the body of the apparatus.

[0056] Next, the first and second plasma treatment portions 4A and 4Bwill be described with reference to FIG. 8. These two plasma treatmentportions have the same functions, and only one or both of them is or areused according to a work load. In FIG. 8 showing the A-A section of FIG.2, an opening 51 a is provided in a side surface of a vacuum chamber 51.The opening 51 a is used for carry-in and carry-out of the semiconductorwafer 11, and has such a size as to allow the wafer holding portion 17holding the semiconductor wafer 11 to come in and go out therethrough.The opening 51 a has an up-and-down gate 56, and the gate 56 is bound toa rod 57 a of a cylinder 57. By driving the cylinder 57, the gate 56 israised or lowered to open or close the opening 51 a.

[0057] Openings 51 b and 51 c are provided in a ceiling surface and abottom surface, respectively, of the vacuum chamber 51. A supportportion 52 a of an upper electrode 52 is inserted into the opening 51 bvia a vacuum-tight bearing 51 e so as to be movable upward and downward.The support portion 52 a is bound to an electrode raising and loweringdrive portion 55, and the upper electrode 52 is raised and lowered bydriving the electrode raising and lowering drive portion 55.

[0058] Many gas ejection ports 52 b are provided in a lower surface ofthe upper electrode 52, and the gas ejection ports 52 b are connected toa gas supply portion 54 via a borehole 52 c provided inside the supportportion 52 a. The gas supply portion 54 supplies a mixed gas for plasmageneration which consists essentially of a fluorine-based gas such asCF₄ and oxygen, or a gas mixture of CF₆ and He.

[0059] A support portion 58 a of a lower electrode 58 is insertedvacuum-tight into the opening 51 c in the bottom surface of the vacuumchamber 51 via an insulator 53. Many attraction holes 58 b are providedin an upper surface of the lower electrode 58, and the attraction holes58 b are connected to a suction control portion 60 via a borehole 58 cprovided inside the support portion 58 a. The suction control portion 60is driven to perform vacuum suction through the attraction holes 58 b,thereby vacuum attracting the semiconductor wafer 11 to the uppersurface of the lower electrode 58 and holding it thereon. On the otherhand, the suction control portion 60 is driven to impart a positivepressure to the attraction holes 58 b, thereby releasing the attractedand held semiconductor wafer 11 from the attracted state.

[0060] A cooling hole 58 d is provided inside the lower electrode 58,and the cooling hole 58 d is connected to an electrode cooling portion61 via a borehole 58 e inside the support portion 58 a. The electrodecooling portion 61 is driven to circulate a refrigerant in the coolinghole 58 d, whereby heat generated during plasma treatment is transferredfrom the lower electrode 58 to the refrigerant. Thus, an abnormal risein the temperature of the lower electrode 58 is prevented, so thatdamage to the protective film 11 a of the semiconductor wafer 11 borneon the lower electrode 58 due to heat can be prevented.

[0061] An exhaust hole 51 d is provided in the vacuum chamber 51, andthe exhaust hole 51 d is connected to a gas exhaust portion 59 via apipe connector 51 f. By driving the gas exhaust portion 59, the spaceinside the vacuum chamber 51 is vacuum exhausted. The lower electrode 58is electrically connected to a high frequency power source portion 62via the support portion 58 a. The upper electrode 52 is connected to aground portion 52 d via the support portion 52 a, and a high frequencyvoltage is applied between the upper electrode 52 and the lowerelectrode 58 opposed to each other, by driving the high frequency powersource portion 62.

[0062] In plasma treatment, the vacuum chamber 51 is closed and itsinterior is vacuum exhausted, with the semiconductor wafer 11 beingborne on and held by the lower electrode 58. Then, a high frequencyvoltage is applied between the upper electrode 52 and the lowerelectrode 58, with a mixed gas for plasma generation being supplied fromthe gas supply portion 54 into the vacuum chamber 51. By this measure, aplasma discharge occurs between the upper electrode 52 and the lowerelectrode 58. The etching effect of the resulting plasma etches theupper surface of the semiconductor wafer 11 to thin the semiconductorwafer 11.

[0063] The gas supply portion 54, electrode raising and lowering driveportion 55, gas exhaust portion 59, suction control portion 60,electrode cooling portion 61, and high frequency power source portion 62are controlled by the control portion (not shown) of the presentapparatus, whereby the above-mentioned plasma treatment action isperformed. At this time, data on the gas flow rate are transmitted fromthe gas supply portion 54 to the control portion, data on the chamberinternal pressure are transmitted from the gas exhaust portion 59 to thecontrol portion, and data on the refrigerant temperature (i.e., theelectrode temperature) are transmitted from the suction control portion60 to the control portion. Based on these data, the control portioncontrols plasma treatment actions.

[0064] The semiconductor wafer processing apparatus is constituted asdescribed above, and thinning of the semiconductor wafer will bedescribed. This thinning is performed after the protective film 11 a isformed on the circuit-formed surface of the semiconductor wafer 11having a plurality of semiconductor devices built therein. Thesemiconductor wafer 11 is supplied in a state in which it isaccommodated into the magazine 2A (2B), with the protective film 11 afacing upward, as shown in FIG. 3. The semiconductor wafer 11 iswithdrawn, with the protective film 11 a side being vacuum attracted tothe wafer holding portion 17, as shown in FIG. 3. The wafer holdingportion 17 having the semiconductor wafer 11 attracted to and held byits lower surface is moved to the precenter portion 5 by the robotmechanism of the third wafer transport portion 3.

[0065] The wafer holding portion 17 is rotated about its axis to turnthe semiconductor wafer 11, which has been attracted to and held by thewafer holding portion 17, upside down. As a result, the semiconductorwafer 11 comes into a state in which it is attracted to and held by theupper surface of the wafer holding portion 17, with the protective film11 a facing downward, as shown in FIG. 5. Then, the wafer holdingportion 17 is lowered, whereby the semiconductor wafer 11 is borne onthe bearing table 20, with the protective film 11 a facing downward.Then, when the wafer holding portion 17 has retreated from inside thegroove portion 21, the positioning pawls 22 a push the outer peripheralportion of the semiconductor wafer 11 toward the center from threedirections. In this manner, alignment of the semiconductor wafer 11,i.e., its centering action, is performed.

[0066] Then, the semiconductor wafer 11 aligned by the centering actionis picked up by the attracting head 25A of the first wafer transportportion 9A, and passed on to the grinding portion 6 as shown in FIG. 6.That is, the attracting head 25A is moved to the wafer transferposition, where the semiconductor wafer 11 is transferred onto the chucktable 7 a.

[0067] Then, mechanical grinding by the grinding portion 6 is carriedout. First, the chuck table 7 a holding the semiconductor wafer 11 ismoved to the rough grinding station below the first grinding unit 8A,and rough grinding with the grindstone 31A is performed there. Then, thechuck table 7 a is moved to the finish grinding station, where finishgrinding using the grindstone 31B of finer abrasive grains is performedby the second grinding unit 8B. At this time, the semiconductor wafer 11is thinned to a dimension greater by a predetermined thickness than apredetermined target thickness dimension, namely, a sum of the targetthickness and a dry etching margin set in the range of 3 μm to 50 μm.

[0068] When finish grinding is completed, the chuck table 7 a holdingthe semiconductor wafer 11 is moved again to the wafer transfer stationby the index rotation of the turn table 7. This semiconductor wafer 11is picked up by the attracting head 25B of the second wafer transportportion 9B, and is moved to the wafer cleaning portion 10 by turning thetransport arm 24B. Thus, the second wafer transport portion 9B serves asa before-cleaning transport portion for withdrawing the semiconductorwafer 11 after grinding from the grinding portion 6 and passing it on tothe wafer cleaning portion 10.

[0069] During the carry-out action for the semiconductor wafer 11,fracture strength is reinforced even if a mechanical damaged layer hasbeen generated by mechanical grinding, since the protective film 11 a isformed in the semiconductor wafer 11 according to the presentembodiment. Thus, breakage of the semiconductor wafer 11 duringtransport can be prevented.

[0070] Next, the cleaning action at the wafer cleaning portion 10 willbe described in accordance with a flow shown in FIG. 11. With the coverportion 36 being lowered in FIG. 7, the transport arm 24B of the secondwafer transport portion 9B is turned to bring the semiconductor wafer11, held by the attracting head 25B, into the cleaning frame portion 35and place it on the rotary support portion 40 (ST1).

[0071] Then, the semiconductor wafer 11 is attracted to and held by therotary support portion 40 by vacuum suction through the attraction holes40 a (ST2), and the attraction of the semiconductor wafer 11 by theattracting head 25B is released (ST3). After the transport arm 24B isretreated to the outside, the cover portion 36 is raised (ST4). As aresult, the semiconductor wafer 11 has its surroundings closed insidethe cleaning frame portion 35, so that ejection of the cleaning fluidbecomes possible.

[0072] Then, the motor 44 is driven to rotate the rotary support portion40 and spin the semiconductor wafer 11 (ST5). In this state, thecleaning fluid is jetted through the cleaning nozzle 47 (ST6), andejection of the cleaning fluid is stopped after a lapse of apredetermined cleaning time (ST7). Then, air is blown through the airnozzle 49 (ST8) to carry out hydro-extraction and drying of the uppersurface of the semiconductor wafer 11. After a lapse of a predeterminedtime, blowing of air is stopped (ST9), whereafter the rotation of therotary support portion 40 is stopped (ST10). By this procedure,cleaning, hydro-extraction, and drying are completed.

[0073] Then, the cover portion 36 is lowered (ST11), whereafter therobot mechanism of the third wafer transport portion 3 is driven toadmit the wafer holding portion 17 into the cleaning frame portion 35(ST12). Then, the upper surface of the semiconductor wafer 11 isattracted by the attraction holes 17 a of the wafer holding portion 17,and the attraction by the attraction holes 40 a of the rotary supportportion 40 is released (ST13). Then, the wafer holding portion 17picking up the semiconductor wafer 11 is raised, and brought out of thecleaning frame portion 35 (ST14).

[0074] Then, the semiconductor wafer 11 rid of foreign matter on thesurface by cleaning is moved to the first plasma treatment portion 4A orthe second plasma treatment portion 4B, where plasma etching (dryetching) is performed. The plasma etching is intended to plasma etch thesurface of the semiconductor wafer 11, which has been thinned bymechanical grinding to the dimension thicker than the target thicknessby the dry etching margin set in the range of 3 μm to 50 μm, to removethe dry etching margin, thereby thinning the semiconductor wafer 11 tothe target thickness.

[0075] When finish grinding is performed using a #3000 to #4000grindstone, the dry etching margin is desirably set at about 5 μm to 6μm. By so doing, the percentage of application of mechanical grinding,which is excellent in the grinding efficiency, can be maximized toimprove the work efficiency. Also, a mechanical damaged layer (generally3 μm to 5 μm) formed by finish grinding can be removed completely.Consequently, the work efficiency and the quality after removal can bothbe ensured.

[0076] The plasma etching will be described with reference to FIGS. 9(a)to 9(b) and 10(a) to 10(b). As shown in FIG. 9(a), the wafer holdingportion 17 having the cleaned semiconductor wafer 11 attracted to andheld by the lower surface thereof is moved from the wafer cleaningportion 10 to a space beside the opening 51 a of the vacuum chamber 51by the robot mechanism of the third wafer transport portion 3. At thistime, the gate 56 is lowered to open the opening 51 a, while the upperelectrode 52 is raised by the electrode raising and lowering driveportion 55 to widen the spacing between the upper electrode 52 and thelower electrode 58. The widened spacing between the upper electrode 52and the lower electrode 58 is intended to avoid an impediment totransport of the wafer by the third wafer transport portion 3. The thirdwafer transport portion 3 serves as an after-cleaning transport portionfor withdrawing the semiconductor wafer 11 after cleaning from the wafercleaning portion 10, and passing it on to the plasma treatment portion4A or 4B.

[0077] Then, as shown in FIG. 9(b), the wafer holding portion 17 isadmitted into the vacuum chamber 51 via the opening 51 a, and thenlowered to place the semiconductor wafer 11, held by the lower surfaceof the wafer holding portion 17, on the upper surface of the lowerelectrode 58. Then, the attraction by the wafer holding portion 17 isreleased, and at the same time, the protective film 11 a of thesemiconductor wafer 11 is attracted to and held by the attraction holes58 b of the lower electrode 58. The plasma treatment portions 4A and 4Bare arranged such that during the carriage of the semiconductor wafer 11into and out of the plasma treatment portion 4A or 4B, the origin 0 islocated on a line of extension of the carry-in and carry-out center lineLa or Lb of the plasma treatment portion 4A or 4B (see FIG. 2). Thus,the carry-in and carry-out actions with a high directional accuracy canbe achieved.

[0078] Then, the wafer holding portion 17 is raised and retreated to theoutside. Then, as shown in FIG. 10(a), the cylinder 57 is driven toraise the gate 56, shutting the vacuum chamber 51. Then, the electroderaising and lowering drive portion 55 is driven to lower the upperelectrode 52, thereby setting the distance between the lower surface ofthe upper electrode 52 and the upper surface of the lower electrode 58at a predetermined interelectrode distance D suitable for plasmaetching, as shown in FIG. 10(b).

[0079] In this state, the aforementioned plasma etching treatment isperformed. That is, after the interior of the vacuum chamber 51 isevacuated, a mixture of a fluorine-based gas and an oxygen gas, or amixture of a fluorine gas and a helium gas is ejected as a plasmageneration gas from the gas ejection ports 52 b in the lower surface ofthe upper electrode 52, and the interior of the vacuum chamber 51 ismaintained at a predetermined gas pressure. In this state, a highfrequency voltage is applied between the upper electrode 52 and thelower electrode 58. By this measure, a plasma discharge is generated inthe space between the upper electrode 52 and the lower electrode 58. Bythe action of active substances formed by the plasma discharge, thesilicon on the surface of the semiconductor silicon is removed.

[0080] The plasma etching treatment is performed continuously until thesemiconductor wafer 11 reaches a target thickness. By this treatment,the mechanical damaged layer produced on the surface of thesemiconductor wafer 11 during the mechanical grinding step is removed.The microcrack introduction layer is usually formed with a thickness of3 μm to 5 μm. Thus, the semiconductor wafer 11 is mechanically ground toa dimension taking into consideration the mechanical damaged layer addedto the target thickness as stated earlier. Then, the thicknesscorresponding to the mechanical damaged layer is removed by plasmaetching, whereby the mechanical damaged layer is completely eliminated,and the semiconductor wafer 11 is processed to the desired thickness.

[0081] The semiconductor wafer 11 after completion of plasma etching iswithdrawn by the wafer holding portion 17 of the third wafer transportportion 3, and accommodated to the same position of the magazine 2A (or2B) of the wafer accommodating portion 2 from which the semiconductorwafer 11 was withdrawn. This action is continuously repeated for othersemiconductor wafers 11. In this transport of the semiconductor wafer 11after thinning, breakage of the semiconductor wafer 11 does not occur,because the damaged layer has been completely eliminated as statedabove, and thus the fracture strength of the semiconductor wafer 11 hasbeen improved.

[0082] According to the present embodiment, as described above, breakageoccurring in the manufacturing process, such as during transport of thesemiconductor wafer 11, due to microcracks, can be prevented, andprocessing yield can be increased. In the present embodiment, moreover,the respective portions in charge of respective functions, such asmechanical grinding, cleaning, and removal of the damaged layer, areconnected by the single robot mechanism. Thus, the area for installationof equipment can be reduced to cut down on the equipment cost.Furthermore, the number of changed grippings of the semiconductor wafer11 during transport can be minimized in comparison with a conventionalsystem, i.e., a system for transferring a semiconductor wafer among aplurality of separate devices by use of transport means such as a robot.Hence, the aforementioned processing yield can be further increased bydecreasing the probability of breakage occurrence of the semiconductorwafer during handling.

[0083] According to the semiconductor wafer processing apparatusillustrated in the present embodiment, moreover, the regions for thegrinding portion 6 and the other respective portions are disposedseparately on the common base portion 1, and transfer of thesemiconductor wafer 11 is performed between these portions by separatetransfer mechanisms. That is, the transport of the semiconductor wafer11 in a contaminant-adhered state in the work region (see the rear halflb shown in FIGS. 1 and 2) in which a grinding liquid is used andadhesion of contaminant such as grinding grains is unavoidable, and thetransport of the semiconductor wafer 11 in a clean state in the cleanroom region (see the front half 1 a shown in FIGS. 1 and 2) for plasmaetching treatment for which a high degree of cleanness is required ofthe object to be treated are performed separately by separate transportmechanisms.

[0084] Thus, the transport mechanism in the clean room region is notcontaminated by adhesion of contaminant. In plasma etching treatmentaimed at removing the mechanical damaged layer, therefore, the surfaceof the semiconductor wafer 11 is free from adhesion of foreign matterwhich inhibits the etching effect, so that the damaged layer on thesurface of the semiconductor wafer 11 can be completely eliminated, andthe fracture strength can be enhanced.

[0085] The present invention is not limited to the above-describedembodiments, and various changes and modifications may be made. In thepresent embodiment, for example, mechanical grinding is performed in twostages, the rough grinding step and the finish grinding step, but thefinish grinding step may be omitted. In this case, a coarse grindstoneis used for grinding, so that the depth of the damaged layer on theupper surface of the wafer is 10 μm or more. Thus, the dry etchingmargin measuring about 50 μm is left, and the remainder is processed bydry etching to the target thickness. By so doing, the damaged layer canbe removed completely. By performing mechanical grinding in a singlestage involving only the rough grinding step, the grinding portion canbe downsized, and a semiconductor wafer processing apparatus with asmall installation floor area can be actualized.

[0086] In the present embodiment, furthermore, the precenter portion 5and the first wafer transport portion 9A are disposed in the firstquadrant of the orthogonal coordinate system, while the second wafertransport portion 9B and the wafer cleaning portion 10 are disposed inthe second quadrant. However, these positions may be interchanged, andthe second wafer transport portion 9B and the wafer cleaning portion 10may be disposed in the first quadrant.

[0087] In the present embodiment, moreover, there is shown an example inwhich the damaged layer removal treatment portion uses dry etching byplasma treatment. However, this example is not limitative, and theremoval treatment portion may rely on wet etching for etch removing thedamaged layer with the use of a chemical liquid such as hydrofluoricacid or nitric acid. That is, a wet etching treatment portion may bedisposed instead of the first and second plasma treatment portions 4Aand 4B. The wet etching treatment portion may be a spin coater which isused in the step of forming a circuit in a semiconductor wafer.

[0088] According to the present invention, a grinding portion formechanically grinding a semiconductor wafer, a wafer cleaning portionfor receiving and cleaning the semiconductor wafer after grinding, adamaged layer removal treatment portion for removing a damaged layer inthe semiconductor wafer after cleaning, and a wafer transport mechanismhaving a robot mechanism on a polar coordinate system for transferringthe semiconductor wafer between the grinding portion, the wafer cleaningportion, and the damaged layer removal treatment portion are provided inthe same apparatus. Thus, the number of changed grippings of thesemiconductor wafer can be minimized, breakage of the semiconductorwafer can be prevented to increase the processing yield, and theequipment can be made compact.

What we claim is:
 1. A semiconductor wafer processing apparatus forgrinding a surface of a semiconductor wafer to thin the semiconductorwafer, comprising: a grinding portion for mechanically grinding thesemiconductor wafer; a wafer cleaning portion for cleaning thesemiconductor wafer after mechanical grinding; a damaged layer removaltreatment portion for removing a damaged layer, caused to thesemiconductor wafer by mechanical grinding, after cleaning by the wafercleaning portion; and a wafer transport mechanism for transferring thesemiconductor wafer between the grinding portion, the wafer cleaningportion, and the damaged layer removal treatment portion.
 2. Thesemiconductor wafer processing apparatus of claim 1, including aprecenter portion for centering the semiconductor wafer, and wherein thesemiconductor wafer, which has been centered by the precenter portion,is supplied to the grinding portion by the wafer transport mechanism. 3.The semiconductor wafer processing apparatus of claim 1, including anstocker for accommodating the semiconductor wafer before processingwhich is to be supplied to the grinding portion and/or the semiconductorwafer after processing which has been withdrawn from the damaged layerremoval treatment portion.
 4. The semiconductor wafer processingapparatus of claim 1, wherein the wafer transport mechanism includes arobot mechanism on a polar coordinate system.
 5. The semiconductor waferprocessing apparatus of claim 1, wherein the wafer transport mechanismincludes a before-cleaning transport portion for withdrawing thesemiconductor wafer after mechanical grinding from the grinding portion,and passing the semiconductor wafer on to the wafer cleaning portion,and an after-cleaning transport portion for withdrawing thesemiconductor wafer after cleaning from the wafer cleaning portion, andpassing the semiconductor wafer on to the damaged layer removaltreatment portion.
 6. The semiconductor wafer processing apparatus ofclaim 1, wherein the damaged layer removal treatment portion is a plasmatreatment portion for etching the damaged layer by plasma treatment. 7.The semiconductor wafer processing apparatus of claim 1, wherein thedamaged layer removal treatment portion is a wet etching treatmentportion for etching the damaged layer with a chemical liquid.
 8. Thesemiconductor wafer processing apparatus of claim 1, wherein the wafertransport mechanism comprises a first wafer transport portion forholding the semiconductor wafer from the precenter portion and bringingthe semiconductor wafer onto the grinding portion, a second wafertransport portion for withdrawing the semiconductor wafer ground by thegrinding portion and transporting the semiconductor wafer to the wafercleaning portion, and a third wafer transport portion having a robotmechanism on a polar coordinate system for transferring thesemiconductor wafer between the precenter portion, the wafer cleaningportion, and the damaged layer removal treatment portion, and thedamaged layer removal treatment portion is disposed in a third quadrantand a fourth quadrant of an orthogonal coordinate system in which anorigin of the polar coordinate system of the robot mechanism is a commonorigin and a direction of the grinding portion is a Y-axis positivedirection, and such that the origin of the polar coordinate system ispositioned on a line of extension of a semiconductor wafer carry-in andcarry-out center line of the damaged layer removal treatment portion. 9.The semiconductor wafer processing apparatus of claim 8, wherein thestocker for accommodating the semiconductor wafer before processingwhich is to be supplied to the grinding portion and/or the semiconductorwafer after processing which has been withdrawn from the damaged layerremoval treatment portion is provided at a position at which the wafercan be brought in and brought out by the third wafer transport portion.10. The semiconductor wafer processing apparatus of claim 8, wherein thecleaning portion is disposed in one of the first quadrant and the secondquadrant of the orthogonal coordinate system.
 11. The semiconductorwafer processing apparatus of claim 10, wherein the precenter portion isdisposed in a quadrant of the coordinate system on a side opposite tothe cleaning portion, with the Y-axis of the coordinate system beinginterposed between the presenter portion and the cleaning portion.
 12. Asemiconductor wafer processing method for thinning a semiconductor waferto a target thickness, including the steps of: mechanically grinding aside of the semiconductor wafer opposite to a surface thereof, where acircuit has been formed, by a grinding portion; withdrawing thesemiconductor wafer after mechanical grinding from the grinding portion,and passing the semiconductor wafer on to the wafer cleaning portion;cleaning the semiconductor wafer passed on to the wafer cleaningportion; withdrawing the semiconductor wafer after cleaning from thewafer cleaning portion, and passing the semiconductor wafer on to adamaged layer removal treatment portion; and removing a damaged layer,caused by the mechanical grinding, in the damaged layer removaltreatment portion.
 13. The semiconductor wafer processing method ofclaim 12, wherein the damaged layer removal treatment portion is aplasma treatment portion for etching the damaged layer by plasmatreatment.
 14. The semiconductor wafer processing method of claim 13,further comprising grinding the semiconductor wafer by mechanicalgrinding to a thickness being a sum of the target thickness and a dryetching margin set in a range of 3 μm to 50 μm, and removing a remainderof the semiconductor wafer by dry etching using plasma treatment. 15.The semiconductor wafer processing method of claim 14, wherein thesemiconductor wafer consists essentially of silicon.
 16. Thesemiconductor wafer processing method of claim 13, wherein after thesemiconductor wafer is ground by the mechanical grinding, thesemiconductor wafer is cleaned with a liquid before dry etching isperformed.
 17. The semiconductor wafer processing method of claim 16,wherein the liquid is water.
 18. The semiconductor wafer processingmethod of claim 12, wherein the damaged layer removal treatment portionis a wet etching treatment portion for etching the damage layer with achemical liquid.
 19. The semiconductor wafer processing method of claim12, wherein mechanical grinding and removal of the damaged layer areperformed, with a protective film being formed on the surface of thesemiconductor wafer where the circuit has been formed.